1. Field of the Invention
The present invention relates to a vertical field effect transistor, and more particularly to a vertical field effect transistor having high power and high speed switching characteristics.
2. Description of the Related Art
Power source devices that have conventionally been used for general purposes or for industrial purposes have been made more and more compact in size and economical in cost by increasing a frequency as typified by switching regulators, and high output performance as well as high speed switching performance have been required for switching transistors used for such devices.
Generally, vertical field effect transistors (hereinafter referred to as "VMOSFETs") having the structure wherein a plurality of sources and gates are formed on the upper surface of a semiconductor substrate and connected in parallel with each other while a drain electrode is formed on the bottom surface. Current flows through the substrate in the thickness direction to provide a high power and a high switching speed The VMOSFETs have been used as the switching transistors of the kind described above.
However, since the VMOSFETs of this kind have a large on-resistance, a high power switching current can be hardly obtained, and various proposals for improving the drawback have been made in order to attain higher power switching by obtaining a small on-resistance.
FIG. 1 is a sectional view of a semiconductor chip having VMOSFETs as the first conventional example. This was disclosed in Japanese Patent Laid-Open No. 52-106688 A high impurity concentration n.sup.+ connection region 3a is formed between two n.sup.+ source regions 6 and below an oxide film of a gate electrode 7 so as to eliminate degradation of frequency characteristics by reducing an internal resistance and thus to improve transconductance. Incidentally, a drain electrode 10 is formed on the back of the substrate.
FIG. 2 is a sectional view of a semiconductor chip and shows the second conventional example. FIGS. 3(a) and 3(b) are diagrams of drain current characteristics before and after the improvement by this second conventional example, respectively, when the gate voltage V.sub.G of VMOSFET is changed This VMOSFET was proposed in U.S. Pat. No. 4,376,286 and U.S. Pat. No. 4,593,302. In the same way as in the first conventional example described above, a high impurity concentration n.sup.+ source region 3a is formed below the gate electrode 7 and between the n source regions 6 in order to reduce on-resistance The improvement is attained from the diagram shown in FIG. 3(a) to the diagram shown in FIG. 3(b).
The broken line 101 in FIG. 9 represents the distribution of the impurity concentration in the n.sup.+ connection region 3a in the longitudinal direction A in the first and second conventional examples shown in FIG. 1 and FIG. 2. As shown in the diagram, the concentration is the highest near the surface of the semiconductor substrate and becomes lower with an increase in depth. In this manner on-resistance is reduced.
In the conventional VMOSFETs described above, since the impurity concentration of the n.sup.+ connection region 3a below the gate oxide film is the highest on the surface of the semiconductor substrate and becomes lower with an increase in depth, on-resistance becomes small and high power switching can be achieved. However, the following problems occur because the impurity concentration of the connection region 3a near the surface is the highest.
FIG. 4 is a schematic sectional view of a semiconductor chip and shows the formation state of a depletion layer in the conventional example When a bias voltage is applied to the drain electrode 10, there occurs the problem in which the depletion layer 111 changes to a depletion layer 112 and curves more sharply towards the gate 7 as the applied voltage becomes larger, and the field strength becomes larger, thereby causing degradation of the withstand voltage. Moreover, since the depletion layer cannot spread and becomes narrow, a parasitic capacitance also becomes large to lower the switching speed.